This application claims priority to German Patent Application No. 101 54 249.6, filed on Nov. 5, 2001, the contents of which are hereby incorporated by reference into this application as if set forth herein in full.
This invention relates generally to analog/digital converters.
Analog/digital converters, also referred to as AD converters, or ADC, are used to convert an input voltage into a digitally-coded number proportional to the input voltage. The structure of the circuitry used in the AD conversion process depends on the conversion method/technique that is used. A distinction is drawn among conversion methods, namely the parallel method, the weighing method, and the counting method. The choice of the conversion method to be used depends, on the one hand, on the desired resolution and, on the other hand, on the desired converter frequency.
Integrated, rapid AD converters are normally operated using the parallel method. These so-called xe2x80x9cflash convertersxe2x80x9d simultaneously compare an input analog voltage to a multitude of graduated reference voltages and determine the two reference voltages between which the input voltage lies. In this manner, a complete, digital number is obtained in a single operating step. A large number of comparators, which represent the speed-limiting element in such circuits, are provided to compare the input voltage with the graduated reference voltages. On the output end, the comparators are connected to a priority decoder, which converts the thermometer-like code of the comparator states into a binary coded number.
The principle of the parallel method of AD conversion described above is described, for example, in Tietze, Schenk: Semiconductor Circuit Technology, 10th edition, pages 774 to 777.
One object of the present invention is to provide an analog/digital converter that is suitable for higher speed AD conversion.
According to the invention, this object is achieved with an analog/digital converter that includes an input for supplying an input voltage; an input for supplying a reference voltage; an input for supplying a clock signal; a first transfer circuit, which is connected to the input for supplying an input voltage and to the input for supplying a clock signal and provides, at its output, an input clock signal with a phase delay dependent on the input voltage; a second transfer circuit, which is connected to the input for supplying the reference voltage and to the input for supplying a clock signal and provides, at its output, a phase delay dependent on the reference voltage; and a comparator, which is connected to the first and second transfer circuit for transmitting input clock and reference clock signals and, dependent on a phase comparison of said signals, delivering a digital output signal.
The specified analog/digital converter is based on the principle of using at least one comparator to compare phase delays, which correspond to the input voltage to be converted or to the reference voltage(s), which may, if applicable, be graduated. In other words, according to this principle, a comparison is made of phase differences instead of voltage differences, with the phase differences being derived from voltage differences.
The assignment of input voltages to phase shifts, which, in the present invention, are phase shifts of a clock signal, is accomplished using the transfer circuits described above. The transfer circuits may be constructed as inverters that are operated unilaterally and in degenerative fashion by an additional component.
The comparator, which can advantageously be constructed using digital switching technology, switches to a logical state, depending on the difference between the phase delays of the input signal and the reference signal. According to the present invention, a phase difference may be defined as the difference between the phase delays of the input clock and reference clock signals, each with respect to the input-end clock signal.
As is commonly the case with AD converters that operate in accordance with the parallel method, the AD converter described above can be further developed into a multi-stage parallel converter or flash converter by adding additional converter stages. The combinatorial logic required to achieve this objective, which connects the outputs of the comparators to one another, may be designed to include the scanning-hold circuits, analogous to conventional parallel converters.
Thus, the AD converter described above does not operate, as has been customary until now, by comparing voltages or currents, but instead compares phase differences derived from these voltages or currents. This, in comparison to prior art AD converters, which operate in accordance with the parallel method, allows for a significant increase in speed and/or suitability for use with substantially higher frequencies.
According to a preferred embodiment of the present invention, the comparator features a means for storing of the output signal. The means for storing, in one embodiment, can be a clock-operated D-flip-flop.
According to another embodiment of the invention, the analog/digital converter may include several comparators, to the respective input ends of which are assigned a first and second transfer circuit. In addition, the AD converter may include a priority decoder, which connects the outputs of the comparators with one another and delivers a digitally-coded and therefore discrete-value signal, which is proportional to the input voltage. Furthermore, the AD converter may feature a reference voltage network, which supplies reference voltages graduated relative to one another to the second transfer circuit.
Analogous to conventional parallel converters, the reference voltage may be divided using, e.g., a resistor network, into equidistant partial voltages. Each of these partial voltages may be supplied to a respective comparator through a respective second transfer circuit. The input voltage itself may be supplied to each of the comparators through a respective first transfer circuit.
To achieve a high degree of circuit symmetry, the first and second transfer circuits can have an identical circuit structure. The electronic components used for the first and second transfer circuits may have a low pairing tolerance, i.e., a high degree of matching.
Also analogous to conventional parallel converters, the priority decoder analyzes the output signals of n (nxe2x89xa71) comparators, of which, for example, comparators 1 to i deliver a high level and comparators i+1 to n deliver a low level (or vice-versa), and convert this result, the so-called thermometer code, into a binary code.
According to another embodiment of the present invention, the comparator may be formed using a bistable trigger circuit. The comparator can, in an especially simple manner, be constructed as an RS-flip-flop, executed by countercoupling two logical NAND gates. According to another embodiment of the present invention, each of the transfer circuits comprises a control input, which is connected to the input for supplying a clock signal. The inverter can be operated as a so-called degraded inverter, in which the rising or falling clock edge of an input clock signal is phase-delayed dependent on an applied control signal, namely the input voltage or the reference voltage.
According to another embodiment of the present invention, each of the transfer circuits comprises a voltage-controlled component, which is connected to the inverter stage for adjustment of the phase delay and features a control input for supplying input or reference voltage. The voltage-controlled component can, for example, be formed as a voltage-controlled resistor or as a voltage-controlled current source, either of which is connected in series in the load current path of the inverter. Alternatively, a voltage-dependent capacity, for example, can be connected to the output of the inverter stages, with the control voltage, i.e., the input or reference voltage, being supplied to the open lead of the inverter stages.
According to another embodiment of the present invention, the first and second transfer circuits are further developed with a shared, for example, symmetrically formed input stage for supplying input or reference voltage, with, for example, the symmetrically or differentially formed input stage being connected to the respective inverter stages by way of current reflectors.
According to another embodiment, the invention is an analog/digital converter that includes a first transfer circuit which receives an input voltage and outputs an output clock signal having a phase delay that is dependent on the input voltage, a second transfer circuit which receives a reference voltage and an input clock signal and outputs a reference clock signal having a phase delay that is dependent on the reference voltage, and a comparator which compares the phase of the output clock signal and the reference clock signal and outputs a digitally-coded output signal that is based on the result of the comparison.
Additional details, advantageous embodiments and further developments of the invention are the subject matter of the dependent claims.
The invention will be explained in greater detail below on the basis of several exemplary embodiments.